In fabricating microelectronic and microelectromechanical devices, it is sometimes desirable (or necessary) to provide a covering structure or cap to protect, contain, and/or complete the microstructures formed on a substrate. The covering structure or cap can be formed by bonding a second wafer atop the first substrate. The second wafer typically includes raised areas or posts for bonding to certain regions of the first substrate and supporting the second wafer. Selected portions of the top wafer are then removed (by cutting or etching, for example) to leave a covering structure (or structures) over the fragile microstructures.
One method used in the art for bonding wafers is known as anodic bonding. A simplified example of such a process is illustrated schematically in FIGS. 1A and 1B. FIG. 1A is a top plan view of a low-conductivity (or semi-insulating) substrate 12 having various structures, devices, and circuits formed thereon. Substrate 12 may comprise a low-conductivity material, or it may comprise a material that is coated or treated to reduce its conductivity (such as a thermal oxide grown on a silicon wafer substrate, for example). FIG. 1B is a cross section taken at section line 1B--1B in FIG. 1A. In FIG. 1B, a second wafer 14 is shown positioned atop substrate 12. For purposes of illustration only, wafer 14 is transparent in FIG. 1A (i.e., not shown) so that the underlying structures can be viewed. The exemplary structures on substrate 12 include circuit lines 16, 17, and 18, and microelectromechanical (MEM) structure 20 supported by a foundation or base 22 bonded to substrate 12. In this example, circuit line 16 forms an electrical connection to MEM structure 20, circuit line 17 serves as a capacitive pickoff for MEM structure 20, and circuit line 18 is an example of another type of connection or interconnect. Wafer 14 includes raised areas 24 that contact substrate 12 at selected regions 26 and 28 to support wafer 14 above structure 20. During anodic bonding of wafer 14 to substrate 12 at contact regions 26 and 28, an electric potential of several hundred to a few thousand volts (typically on the order of 1000 volts, as shown as an example in FIG. 1B) is applied across substrate 12 and wafer 14. Substrate 12 and wafer 14 may also be externally heated during the process. The high electric potential causes current to flow between substrate 12 and wafer 14, which bonds raised areas 24 of wafer 14 at contact regions 26 and 28 of substrate 12. In general, this process yields different mechanical strengths for bond joints between different materials.
During application of a high electric potential across substrate 12 and wafer 14, undesired arcing and flexing, contact, bonding, or other damage can occur, caused by strong electrostatic attraction between objects, such as fragile structure 20, lines 16, 17, and 18, wafer 14, and substrate 12. To prevent damage to fragile structure 20, circuit lines 16, 17, and 18 can be laid out so that they are joined together by slender conductors, such connector lines 32 and 34. With circuit lines 16, 17, and 18 connected by lines 32 and 34, structure 20 and the circuit lines are all at nearly the same electrical potential during anodic bonding of wafer 14 to low-conductivity substrate 12, thereby preventing arcing and damage to fragile structure 20 or circuit lines 16, 17, and 18.
After wafer 14 has been bonded to substrate 12, unneeded portions of wafer 14 can be removed by sawing, laser cutting, etching, or other techniques, leaving covering structures only over selected structures, such as MEM structure 20, as shown in FIGS. 2A and 2B. For proper operation of MEM structure 20, however, circuit lines 16, 17, and 18 must be disconnected from each other to form discrete conductive paths. This can be accomplished by eliminating connector lines 32 and 34 by laser cutting, sawing, etching, or other techniques, as shown in FIG. 3 where trenches 36 and 38 serve to separate the circuit lines. A useful alternative is to place circuit connectors 32 and 34 at perimeter regions of the chip where they are eliminated when individual chips on the substrate are sawed apart. This embodiment avoids wasting chip surface area with temporary connector lines 32 and 34.
A drawback of the foregoing prior art process is that temporary structures such as connector lines 32 and 34 may not be compatible with operation of the final device, and processing steps are usually required at some stage to eliminate them. Depending on the process used to achieve the separation shown in FIGS. 2A and 2B, the size, materials, or interconnect topography requirements for connectors 32 and 34 may be very inconvenient. In addition, the processing steps needed for circuit separation have a negative impact on cost and device yield. Furthermore, until the temporary shorts are eliminated, multiple objects are shorted together and the device cannot be fully tested or operated for its design use. Therefore, there is a need for improved anodic bonding processes for forming covering structures or caps over fragile microelectronic or microelectromechanical structures.